Zynq 7020 technical reference manual

Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq and Zynq are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader FSBL , a bitstream for configuring the programmable logic optional , and a user application.

The boot process is broken into three stages:. If and only if the Zynq was just powered on, the BootROM will first latch the state of the mode pins into the mode register the mode pins are attached to JP5 on the Zybo Z7. If the BootROM is being executed due to a reset event, then the mode pins are not latched, and the previous state of the mode register is used. This means that the Zybo Z7 needs a power cycle to register any change in the programming mode jumper JP5.

Finally, the user application is loaded into memory from the Zynq Boot Image, and execution is handed off to it. The last stage is the execution of the user application that was loaded by the FSBL. For a more thorough explanation of the boot process, refer to Chapter 6 of the Zynq Technical Reference manual.

For information on creating this image please refer to the available Xilinx documentation for these tools. The boot mode is selected using the Mode jumper JP5 , which affects the state of the Zynq configuration pins after power-on. Figure 2. When placed in JTAG boot mode, the processor will wait until software is loaded by a host computer using the Xilinx tools.

After software has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK. This can be done using the Vivado Hardware Server. A feature called DCI Digitally Controlled Impedance is used to match the drive strength and termination impedance of the PS pins to the trace impedance.

On the memory side, each chip calibrates its on-die termination and drive strength using a ohm resistor on the ZQ pin. Due to layout reasons, the two lower data byte groups DQ[], DQ[] were swapped. To the same effect, the data bits inside byte groups were swapped as well. These changes are transparent to the user. During the whole design process the Xilinx PCB guidelines were followed.

The mid-point reference of 0. For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays. Training is done dynamically by the controller to account for board delays, process variations and thermal drift. Optimum starting values for the training process are the board delays propagation delays for certain memory signals.

Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. For more details on memory controller operation, refer to the Xilinx Zynq Technical Reference manual. The key device attributes are:. The Flash memory is used to provide non-volatile code and data storage. The Flash is also commonly used to store non-configuration data needed by the application.

If doing this from a bare-metal application, The flash memory can be freely accessed using standalone libraries included with a Xilinx SDK BSP project. The details of these connections do not need to be known when using the Zybo Z7 Vivado Board files, as they will automatically configure your project to work correctly with the on-board Flash.

The OTP region also includes a factory-programmed read-only bit random number. The very lowest address range [0x00;0x0F] can be read to access the random number. The Zybo Z7 provides a The The PS has a dedicated PLL capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the PL.

The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.

Figure 5. Note that the reference clock output from the Ethernet PHY is used as the MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. The Zybo Z7 provides several different methods of resetting the Zynq device, as described in the following sections. The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset.

For example, the previous break points set by the user remain valid after system reset. The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled.

After changing boot moode jumpers a power cycle is needed to act on the new setting. Drivers are automatically installed in Windows and newer versions of Linux when the Zybo Z7 is attached.

The Zynq presets file available in the Zybo Z7 Resource Center takes care of mapping the correct MIO pins to the UART 1 controller and uses the following default protocol parameters: baud rate, 1 stop bit, no parity, 8-bit character length. The combination of these two features into a single device allows the Zybo Z7 to be programmed, communicated with via UART, and powered from a computer attached with a single Micro USB cable. Figure 7. UART Connections.

The pinout can be seen in Table 8. The SD slot is powered from 3. The connection diagram can be seen on Figure 8. Mapping out the correct pins and configuring the interface is handled by the Zybo Z7 board files, available on the Zybo Z7 resource center.

Both low speed and high speed cards are supported, the maximum clock frequency being 50 MHz. A Class 4 card or better is recommended. The microSD is also commonly used to store non-configuration data needed by the application. The Zybo Z7 should never have a peripheral device and a host device connected to these two connectors at the same time.

Only those experienced at soldering small components on PCBs should attempt this rework. Most USB peripheral devices will work just fine without loading C Note that if your project uses the USB host feature embedded or general purpose , then the Zybo Z7 is very likely to consume more current than is allowed by a USB peripheral, causing it to periodically reset.

To prevent this, power the Zybo Z7 from an external source capable of providing more power. The connection diagram can be seen on Figure If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured. Table The Zynq incorporates two independent Gigabit Ethernet Controllers. Since the MIO bank is powered from 1. Mapping out the correct pins and configuring the interface is handled by the Zybo Z7 Vivado board files.

With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration. Xilinx PCB guidelines also require this delay to be added. On an Ethernet network each node needs a unique MAC address. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address.

Refer to the Flash memory datasheet for information on how to access the OTP regions. When using Petalinux, this is automatically handled in the U-boot boot-loader, and the Linux system is automatically configured to use this unique MAC address. The identifier is also printed on a sticker found on the top-side of the Zybo Z7 right next to the mode jumper JP5 and above the headphone output jack.

When using the Zybo Z7 with a Petalinux generated embedded Linux system, the ethernet port will automatically appear as a network device typically named eth0. This device is used to prevent displays from back-powering the Zybo Z7, and otherwise has no effect on functionality. Thus, simple passive adaptors available at most electronics stores can be used to drive a DVI monitor or accept a DVI input.

The implementation details are outside the scope of this manual. The IP cores for transmitting and receiving are called rgb2dvi and dvi2rgb, respectively. Whenever a sink is ready and wishes to announce its presence, it connects the 5V0 supply pin to the HPD pin. Note this should only be done after a DDC channel slave has been implemented in the Zynq PL and is ready to transmit display data.

The Display Data Channel, or DDC, is a collection of protocols that enable communication between the display sink and graphics adapter source. Only afterwards will video transmission begin.

IP supplied by Digilent in our Github repository vivado-library Digilent github includes DDC support and some pre-defined display descriptor data. A common use case is a TV passing control messages originating from a universal remote to a DVR or satellite receiver. It is a one-wire protocol at 3. The wire can be controlled in an open-drain fashion allowing for multiple devices sharing a common CEC wire. It allows for stereo record and playback at sample rates from 8 kHz to 96 kHz. On the analog side, the codec connects to three 3.

There are two inputs: a mono microphone and a stereo line in. There is one stereo output, the headphone jack. Analog power is provided by a dedicated linear power supply IC5.

The digital interface of the SSM is wired to the programmable logic side of the Zynq. Configuration is done over an I2C bus. The device address of the SSM is b. This master clock will be used by the audio codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired sampling rate. The default settings require a master clock of For other frequencies and their respective configuration parameters, consult the SSM datasheet.

The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals is specified in Table In this mode, the codec generates the proper frequencies for these clocks.

The master clock is always driven out of the Zynq. Audio samples are transmitted MSB first, noted as 1 in the diagram. The digital mute signal MUTE is active-low, with a pull-down resistor. This means that when not used in the design, it will stay low and the analog outputs of the codec will stay muted.

To enable the analog outputs, drive this signal high. To use the audio codec in a design with non-default settings, it needs to be configured over I2C.

The audio path needs to be established by configuring the de multiplexers and amplifiers in the codec. Some digital processing can also be done in the codec. Configuration is read out and written by accessing the register map via I2C transfers. The register map is described in the SSM datasheet. A demo project that uses the Zybo Z7 audio codec in a bare-metal application can be found on the Zybo Z7 Resource Center. The audio codec is also supported in Petalinux generated embedded Linux systems, and will appear as a standard ALSA audio device.

The push-buttons and slide switches are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits a short circuit could occur if a pin assigned to a push-button or slide switch was inadvertently defined as an output. Slide switches generate constant high or low inputs depending on their position.

Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the signal corresponding to one of these colors high will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED , the corresponding signals need to be driven high.

The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color. The Zybo Z has a connector that can be used to power a fan mounted to the included heat sink.

In order to attach the fan to the Zybo Z heat sink, two of the included screws must be tightened into the space between the heat sink fins the heat sink does not contain mounting holes.

The fan must be attached with the label facing down, towards the Zynq device, in order to push the air flow in the correct direction. After mounting the fan, plug the fan into the 3-pin fan connector J14 on the Zybo Z to use it. A Zybo Z with the fan properly attached is shown in Figure Once the fan has been installed and connected, it will always be on when the Zybo Z is turned on.

This generates a pulse with a frequency proportional to the rotation speed of the fan. Visit ZedBoard. Skip to Navigation Skip to Main Content. Toggle SideBar. Xilinx Support Community. Sign in to ask the community.

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